Synthesizable delay with VHDL (One single output pulses)

Try this. It has a new state that hangs the state machine:

begin

process (clk)

begin

if (rising_edge(clk))then

data_out <= '0';

case next_s is

when idle =>

c <= c + 1;

next_s <= delay;

when delay =>

if (c = a) then

data_out <= '1';

c <= c + 1;

end if;

if (c = b) then

data_out <= '0';

next_s <= stopped;

c <= 0;

else

c <= c + 1;

end if;

when stopped =>

data_out <= '0';

end case;

end if;

end process;

end behavioral;