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Altera_Forum's avatar
Altera_Forum
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11 years ago

Synthesizable delay with VHDL (One single output pulses)

Thanks in advance for your nice instructions. What I am doing is producing a single output pulse. It is a simple output but due my little knowledge it becomes complicated for me. What I want in ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

You're inferring a register on data_out. You may assign a default value '0' to it, when conditions ( c = a ) and ( c = b ) don't match.

process..

begin

if( rising_edge(clk)) then

data_out <= '0';

case ....

a reset condition it helps too:

begin

if(clr='1') then

data_out <= '0';

elsif(rising_edge(clk)...