Question on LE

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Hi,

could you see the zip-file at the end of the post ?

Keep attritbute in VHDL :

signal net1 : std_logic;

attribute keep: boolean;

attribute keep of net1: signal is true;

Kind regards

GPK

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ya, i saw it! thanks alot! In my design, I use functions (written as package) so all the arithmetic involved variables rather than signals. only the input and output are declared as signals.

in my case, what should I do to use this keep attribute?

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Hi,

ermm..where can I access the attachment?

regarding this "keep" attribute. Im still not very sure how it is done. Is is applicable to variable?

Regards,

Clare

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Hi,

could you see the zip-file at the end of the post ?

Keep attritbute in VHDL :

signal net1 : std_logic;

attribute keep: boolean;

attribute keep of net1: signal is true;

Kind regards

GPK

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Hi,

I'm not a real VHDL expert, but I have VHDL version of my project attached. Keep in mind that you can also use the "keep" attribute for the signals.

Kind regards

GPK

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Hi,

ermm..where can I access the attachment?

regarding this "keep" attribute. Im still not very sure how it is done. Is is applicable to variable?

Regards,

Clare

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A simple question. In your project, you the AND gates named as and1, and2, and3, and4 and hence they can be chosen as Implement as Output of Logic Cell. But how can it be done in VHDL?

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Hi,

I'm not a real VHDL expert, but I have VHDL version of my project attached. Keep in mind that you can also use the "keep" attribute for the signals.

Kind regards

GPK

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Hi,

I assume that your gate are all 2-input gates. In an FPGA your logic is implemented in LUT.

The LUT has at least 4 input and one output. That means you can implement every logic function with 4 inputs and one output. The fitter will look for ways to fill the LUT's effectively. There is an Assignment (implement as output of logic cell) which could be used to force the Fitter to implement the outputs of the gate in one LUT (Implement as Output of Logic Cell).

I have a small example attached. Maybe this solves your problem.

Kind regards

GPK

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A simple question. In your project, you the AND gates named as and1, and2, and3, and4 and hence they can be chosen as Implement as Output of Logic Cell. But how can it be done in VHDL?

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how is that be done?

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Hi,

rbugalho is right, you could also try to use soome synthesis attribute.

Example:

Verilog

wire net1 /* synthesis keep */;

VHDL

signal net1 : std_logic;

attribute keep: boolean;

attribute keep of net1: signal is true;

Kind regards

GPK

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Using the synthesis attribute "keep" should also provide similar results.

That said, I hope the original poster understood what's going on here.. :)

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how is that be done?

Using the synthesis attribute "keep" should also provide similar results.

That said, I hope the original poster understood what's going on here.. :)

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Hi,

I think this is very helpful. But do I change the (implement as output of logic cell) ??

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Hi,

look into the small testcase. Open the project with Quartus. Open the assignment editor.

You find the editor under : Assignments -> Assignment Editor

Kind regards

GPK