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Altera_Forum's avatar
Altera_Forum
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16 years ago

Question on LE

Dear all, Im wondering if it is possible to have a design that actually has fewer logic gates but took up more LE than another design that has more logic gates? This is happened to my desi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

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A simple question. In your project, you the AND gates named as and1, and2, and3, and4 and hence they can be chosen as Implement as Output of Logic Cell. But how can it be done in VHDL?

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Hi,

I'm not a real VHDL expert, but I have VHDL version of my project attached. Keep in mind that you can also use the "keep" attribute for the signals.

Kind regards

GPK