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Altera_Forum
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16 years ago

Question on LE

Dear all, Im wondering if it is possible to have a design that actually has fewer logic gates but took up more LE than another design that has more logic gates? This is happened to my desi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

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how is that be done?

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Hi,

rbugalho is right, you could also try to use soome synthesis attribute.

Example:

Verilog

wire net1 /* synthesis keep */;

VHDL

signal net1 : std_logic;

attribute keep: boolean;

attribute keep of net1: signal is true;

Kind regards

GPK