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Altera_Forum's avatar
Altera_Forum
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16 years ago

Question on LE

Dear all, Im wondering if it is possible to have a design that actually has fewer logic gates but took up more LE than another design that has more logic gates? This is happened to my desi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

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Hi,

could you see the zip-file at the end of the post ?

Keep attritbute in VHDL :

signal net1 : std_logic;

attribute keep: boolean;

attribute keep of net1: signal is true;

Kind regards

GPK

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ya, i saw it! thanks alot! In my design, I use functions (written as package) so all the arithmetic involved variables rather than signals. only the input and output are declared as signals.

in my case, what should I do to use this keep attribute?