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Hi,
I assume that your gate are all 2-input gates. In an FPGA your logic is implemented in LUT.
The LUT has at least 4 input and one output. That means you can implement every logic function with 4 inputs and one output. The fitter will look for ways to fill the LUT's effectively. There is an Assignment (
implement as output of logic cell) which could be used to force the Fitter to implement the outputs of the gate in one LUT (Implement as Output of Logic Cell).
I have a small example attached. Maybe this solves your problem.
Kind regards
GPK
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A simple question. In your project, you the AND gates named as and1, and2, and3, and4 and hence they can be chosen as Implement as Output of Logic Cell. But how can it be done in VHDL?
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