Question about Custom User HDL

You can only have one read data signal, use the adress signal to multiplex multiples data that you want to read

you select a signal as a write interface but you didnt do any control on it

Thank you for your reply et for this clarification,

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Dude make a HDL block with inputs and outputs and your logic.

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I synthetize my HDL block and it work fine.

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Then integrate it in your SOPC connecting the inputs(data, clock, reset) and outputs(5 highest numbers, maybe a valid signal?) in their respective signals. (take a look at the AVALON INTERFACE/SOPC user guide to see the correct name of the signals).

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And i read AVALON INTERFACE/SOPC "http://www.altera.com/literature/ug/ug_sopc_builder.pdf" but i don't arrived to understand it because isn't simple. If it is possible that you give me a small information or to clarify this. If isn't possible, can your reply to me for the following question:

1- I use avalon memory mapped slave, when i relate each input and output for the following connect i get these two message:

warning: avalon_slave_0: signal read data appears 4 times(only once is allowed)

error: avalon_slave_0 has write interface but no witre control.

what can i do with this message.

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However the calculus won't be done in one clock cycle, it will take X clock cycles + X clock cycle to perform a read in the NIOS2 (i think the total clock cycle number will be small enough for you.. it will probably take 5~10 clock cycles)

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Thank yoy for this inofrmation.

Dude make a HDL block with inputs and outputs and your logic.

Then integrate it in your SOPC connecting the inputs(data, clock, reset) and outputs(5 highest numbers, maybe a valid signal?) in their respective signals. (take a look at the AVALON INTERFACE/SOPC user guide to see the correct name of the signals).

However the calculus won't be done in one clock cycle, it will take X clock cycles + X clock cycle to perform a read in the NIOS2 (i think the total clock cycle number will be small enough for you.. it will probably take 5~10 clock cycles)

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I know this for this reason, i decide to read every clock cycle just one value and insert it, it mean after 32( read an insert) clock cycle, i get 16 value sorted.

This time isn't requirement but i try to execute this code on the minimum of clock cycle, i hope that don't avoid 32 clock cycle.

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Now you are changing your timing requirements.

The simplest implementation is to simply 'sort data as it comes in'. The component interface design should be that you write 16 values to a location, and then read back 5, with those 5 values being the greatest. The internal sorting is what you now have to figure out.

Cheers,

Dave

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You will need to use 16 blocks of on-chip memory, or 8 blocks of dual-port memory if you want to have 16 samples read in one clock.

However, you cannot read the data in one clock, since the inputs are registered, and the outputs are possibly registered.

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I know this for this reason, i decide to read every clock cycle just one value and insert it, it mean after 32( read an insert) clock cycle, i get 16 value sorted.

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Well, you've already blown out your timing by having the data in on-chip RAM, so are you really sure that the two clock cycles is a requirement?

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This time isn't requirement but i try to execute this code on the minimum of clock cycle, i hope that don't avoid 32 clock cycle.

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What is wrong with having a pipeline of comparisons;

- 16 outputs from 16 RAMs

- 8 two input comparisons with 8 outputs

- 4 two input comparisons with 4 outputs

- 2 two input comparisons with 2 outputs

- 1 two input comparison with 1 output

This logic will output the comparison data on every clock, however, it will have a pipeline latency of 5 clocks.

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I'am so sorry i don't understand what do you mean by this?

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The Data come from the onchip memory. Every iteration i will get 16 value from memory, and sorted them, and calculate the threshold.

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You will need to use 16 blocks of on-chip memory, or 8 blocks of dual-port memory if you want to have 16 samples read in one clock.

However, you cannot read the data in one clock, since the inputs are registered, and the outputs are possibly registered.

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This algorithm after two clock cycle, give the 16 input value sorted.

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Well, you've already blown out your timing by having the data in on-chip RAM, so are you really sure that the two clock cycles is a requirement?

What is wrong with having a pipeline of comparisons;

- 16 outputs from 16 RAMs

- 8 two input comparisons with 8 outputs

- 4 two input comparisons with 4 outputs

- 2 two input comparisons with 2 outputs

- 1 two input comparison with 1 output

This logic will output the comparison data on every clock, however, it will have a pipeline latency of 5 clocks.

Unless you have a feedback path, you should consider using pipelined logic ...

Cheers,

Dave

Really thank you very much for this explanation. Now, i understand the differnce.

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The attached file is meaningless without a timing diagram that shows the waveforms used to control this block. This is a good start, but it does not help explaining what you are trying to do.

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This algorithm after two clock cycle, give the 16 input value sorted.

If you need a waveforme, i don't have a problem i will attach it next time.

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So what is the timing requirement; finish in two clocks, or finish in 0.5us?

If its finish in 0.5us, then at 100MHz, this is 50 clocks.

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My design work at 250Mhz. it mean that clock cycle is 0.004us. That's mean the sorted value it will be ready after 0.008us.

For the 0.5us forget it because this time should taken with all of my project, although the sorting is a part for my project. At least not last, the sorting algorithm is critical part of my project. i add on attached file a picture that will more explain the problem.

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If the data that you are finding the highest five values in is continuously streaming into your FPGA, then the highest five values can be read at any time, and they will represent the five highest values that have come in so far.

The search algorithm is not the only important part of the design; where the data comes from is just as important.

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The Data come from the onchip memory. Every iteration i will get 16 value from memory, and sorted them, and calculate the threshold.

Cheers,

Dave

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i confuse between custom instruction and SOPC Component. At first i belive they were the same, if you can that you give me the difference between it. When can i use custon instruction and when i use SOPC component.

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A custom instruction is something that can be inserted into the NIOS II processor pipeline.

An SOPC Component is a memory-mapped component that a NIOS II processor can access.

When you need to use one or the other is application dependent. An example of a custom instruction would be a multiply operation, and an example of a custom component would be a checksum accelerator.

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I will try to explain what i suppose to implement. I have PRC algorithm that contain 16 bloc of SBC( mentionned on the attached file).

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The attached file is meaningless without a timing diagram that shows the waveforms used to control this block. This is a good start, but it does not help explaining what you are trying to do.

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1- the result of this algorithm it valid on two clock cycle.

2- For me i search if i can implement it "Using a NIOS II processor using a custom instruction", if it is possible ok, else i implement it '"Using a NIOS II processor and software, with data in FPGA RAM".

I use this solution because i implement it using c, but it give a big execution time, about 18 microseond. Om my project i have a real time contraint, and my project should be execute on 0.5 microsecond.

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So what is the timing requirement; finish in two clocks, or finish in 0.5us?

If its finish in 0.5us, then at 100MHz, this is 50 clocks.

If the data that you are finding the highest five values in is continuously streaming into your FPGA, then the highest five values can be read at any time, and they will represent the five highest values that have come in so far.

The search algorithm is not the only important part of the design; where the data comes from is just as important.

Try to draw a block diagram of the system design first, and then look at the implementation of each of the components.

Cheers,

Dave

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All of these statements are very confusing.

You are indicating you are using lots of features of Quartus, eg., SOPC components and custom NIOS II instructions, yet none of your explanations make sense. I fear you do not understand any of them.

Why don't you start out by explaining exactly what you are supposed to implement, as well as the constraints on what type of logic you are allowed to do, eg.,

Project:

Determine the five greatest values from 16 input values

Implementation:

a) In pure HDL, with the result valid in one clock

b) In pure HDL, with the result valid in multiple clocks

c) Using a NIOS II processor and software, with data in FPGA RAM

d) Using a NIOS II processor using a custom instruction

If you get to choose the implementation, then start with the simplest, i.e., the software solution (c). Start by writing the code on your desktop computer. Then work on other versions of the code.

Cheers,

Dave

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I'am so sorry, for my explanation.

Yes Dave, i confuse between custom instruction and SOPC Component. At first i belive they were the same, if you can that you give me the difference between it. When can i use custon instruction and when i use SOPC component.

I will try to explain what i suppose to implement. I have PRC algorithm that contain 16 bloc of SBC( mentionned on the attached file). It mean that i need 16 SBC bloc work en parallel.

1- the result of this algorithm it valid on two clock cycle.

2- For me i search if i can implement it "Using a NIOS II processor using a custom instruction", if it is possible ok, else i implement it '"Using a NIOS II processor and software, with data in FPGA RAM".

I use this solution because i implement it using c, but it give a big execution time, about 18 microseond. Om my project i have a real time contraint, and my project should be execute on 0.5 microsecond.

I hope that is clear.

Thank you very much.

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I synthetize my design through quartus II, and on the SOPC builder i add a new component and i call my HDL design. After this he appear to me the next window witch i will relate the signal of my design to tha avalon interface. I am not sur about the link that i make because it appear to me some warning.

My design have 16 input value coding in 16 bits. In reality it come from the RAM through the Nios II processor. If it is possible to relate my design directly with RAM it will be very good, beacuse i don't have any idea that's possible or no.

On my application i need to get the five greatest value of the first 16 memory value. Every time i will make the same think but on the next 16 value. I hope that it is clear.

Actually i just sysnthetize my design and i'am blocked on this step. How should i connect the input to the vavlon, because as i mentionned above, i am not sur about the link that i make this is first.

Second after i connect my custom instruction to the niosII, how i know the adress of every input and output.

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All of these statements are very confusing.

You are indicating you are using lots of features of Quartus, eg., SOPC components and custom NIOS II instructions, yet none of your explanations make sense. I fear you do not understand any of them.

Why don't you start out by explaining exactly what you are supposed to implement, as well as the constraints on what type of logic you are allowed to do, eg.,

Project:

Determine the five greatest values from 16 input values

Implementation:

a) In pure HDL, with the result valid in one clock

b) In pure HDL, with the result valid in multiple clocks

c) Using a NIOS II processor and software, with data in FPGA RAM

d) Using a NIOS II processor using a custom instruction

If you get to choose the implementation, then start with the simplest, i.e., the software solution (c). Start by writing the code on your desktop computer. Then work on other versions of the code.

Cheers,

Dave