--- Quote Start ---
You will need to use 16 blocks of on-chip memory, or 8 blocks of dual-port memory if you want to have 16 samples read in one clock.
However, you cannot read the data in one clock, since the inputs are registered, and the outputs are possibly registered.
--- Quote End ---
I know this for this reason, i decide to read every clock cycle just one value and insert it, it mean after 32( read an insert) clock cycle, i get 16 value sorted.
--- Quote Start ---
Well, you've already blown out your timing by having the data in on-chip RAM, so are you really sure that the two clock cycles is a requirement?
--- Quote End ---
This time isn't requirement but i try to execute this code on the minimum of clock cycle, i hope that don't avoid 32 clock cycle.
--- Quote Start ---
What is wrong with having a pipeline of comparisons;
- 16 outputs from 16 RAMs
- 8 two input comparisons with 8 outputs
- 4 two input comparisons with 4 outputs
- 2 two input comparisons with 2 outputs
- 1 two input comparison with 1 output
This logic will output the comparison data on every clock, however, it will have a pipeline latency of 5 clocks.
--- Quote End ---
I'am so sorry i don't understand what do you mean by this?
Honored Contributor
