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The Data come from the onchip memory. Every iteration i will get 16 value from memory, and sorted them, and calculate the threshold.
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You will need to use 16 blocks of on-chip memory, or 8 blocks of dual-port memory if you want to have 16 samples read in one clock.
However, you cannot read the data in one clock, since the inputs are registered, and the outputs are possibly registered.
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This algorithm after two clock cycle, give the 16 input value sorted.
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Well, you've already blown out your timing by having the data in on-chip RAM, so are you really sure that the two clock cycles is a requirement?
What is wrong with having a pipeline of comparisons;
- 16 outputs from 16 RAMs
- 8 two input comparisons with 8 outputs
- 4 two input comparisons with 4 outputs
- 2 two input comparisons with 2 outputs
- 1 two input comparison with 1 output
This logic will output the comparison data on every clock, however, it will have a pipeline latency of 5 clocks.
Unless you have a feedback path, you should consider using pipelined logic ...
Cheers,
Dave
Honored Contributor
