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I synthetize my design through quartus II, and on the SOPC builder i add a new component and i call my HDL design. After this he appear to me the next window witch i will relate the signal of my design to tha avalon interface. I am not sur about the link that i make because it appear to me some warning.
My design have 16 input value coding in 16 bits. In reality it come from the RAM through the Nios II processor. If it is possible to relate my design directly with RAM it will be very good, beacuse i don't have any idea that's possible or no.
On my application i need to get the five greatest value of the first 16 memory value. Every time i will make the same think but on the next 16 value. I hope that it is clear.
Actually i just sysnthetize my design and i'am blocked on this step. How should i connect the input to the vavlon, because as i mentionned above, i am not sur about the link that i make this is first.
Second after i connect my custom instruction to the niosII, how i know the adress of every input and output.
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All of these statements are very confusing.
You are indicating you are using lots of features of Quartus, eg., SOPC components and custom NIOS II instructions, yet none of your explanations make sense. I fear you do not understand any of them.
Why don't you start out by explaining exactly what you are supposed to implement, as well as the constraints on what type of logic you are allowed to do, eg.,
Project:
Determine the five greatest values from 16 input values
Implementation:
a) In pure HDL, with the result valid in one clock
b) In pure HDL, with the result valid in multiple clocks
c) Using a NIOS II processor and software, with data in FPGA RAM
d) Using a NIOS II processor using a custom instruction
If you get to choose the implementation, then start with the simplest, i.e., the software solution (c). Start by writing the code on your desktop computer. Then work on other versions of the code.
Cheers,
Dave
Honored Contributor
