Question about Custom User HDL

Thank you for your reply et for this clarification,

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Dude make a HDL block with inputs and outputs and your logic.

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I synthetize my HDL block and it work fine.

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Then integrate it in your SOPC connecting the inputs(data, clock, reset) and outputs(5 highest numbers, maybe a valid signal?) in their respective signals. (take a look at the AVALON INTERFACE/SOPC user guide to see the correct name of the signals).

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And i read AVALON INTERFACE/SOPC "http://www.altera.com/literature/ug/ug_sopc_builder.pdf" but i don't arrived to understand it because isn't simple. If it is possible that you give me a small information or to clarify this. If isn't possible, can your reply to me for the following question:

1- I use avalon memory mapped slave, when i relate each input and output for the following connect i get these two message:

warning: avalon_slave_0: signal read data appears 4 times(only once is allowed)

error: avalon_slave_0 has write interface but no witre control.

what can i do with this message.

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However the calculus won't be done in one clock cycle, it will take X clock cycles + X clock cycle to perform a read in the NIOS2 (i think the total clock cycle number will be small enough for you.. it will probably take 5~10 clock cycles)

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Thank yoy for this inofrmation.