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Altera_Forum
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14 years ago

Question about Custom User HDL

Hi, I try to implement a VHDL code as custom user HDL. The component that i need to release is an algorithme that determine the five greatest value for 16 input in one clock cycle. I compile th...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

You can only have one read data signal, use the adress signal to multiplex multiples data that you want to read

you select a signal as a write interface but you didnt do any control on it