Honored Contributor
Honored ContributorReally thank you very much for this explanation. Now, i understand the differnce.
--- Quote Start --- The attached file is meaningless without a timing diagram that shows the waveforms used to control this block. This is a good start, but it does not help explaining what you are trying to do. --- Quote End --- This algorithm after two clock cycle, give the 16 input value sorted. If you need a waveforme, i don't have a problem i will attach it next time. --- Quote Start --- So what is the timing requirement; finish in two clocks, or finish in 0.5us? If its finish in 0.5us, then at 100MHz, this is 50 clocks. --- Quote End --- My design work at 250Mhz. it mean that clock cycle is 0.004us. That's mean the sorted value it will be ready after 0.008us. For the 0.5us forget it because this time should taken with all of my project, although the sorting is a part for my project. At least not last, the sorting algorithm is critical part of my project. i add on attached file a picture that will more explain the problem. --- Quote Start --- If the data that you are finding the highest five values in is continuously streaming into your FPGA, then the highest five values can be read at any time, and they will represent the five highest values that have come in so far. The search algorithm is not the only important part of the design; where the data comes from is just as important. --- Quote End --- The Data come from the onchip memory. Every iteration i will get 16 value from memory, and sorted them, and calculate the threshold. Cheers, Dave --- Quote End ---
