Question about Clock Enable port on D flip flop

I think it is like clock gating at source but per LAB module so you have incoming clock in flip-flop that was gated <-it is what I achieve from reading handbook for Cyclone V. But how will be right? from documentaion it is not really clear.

And it should be an issue for those who writes such bad technical papers 'you have two clocks and three clock-enable', very short explanation. where is third clock?

Really bad clarification in docs for architecture of ALM and LAB in Cyclone V handbook found at web site.

The docs for MAX10 in this case better. but who know except those who develope it?

It is there, it is just not shown in the diagram (no clock gating at all as suggested by alex96)

Page 1-5 from https://www.altera.com/en_us/pdfs/literature/hb/cyclone-v/cv_5v2.pdf

"GPIO pins or internal logic drives the clock enable signal."

) I know that it is not shown at figures but last sentence in pargraph " LAB Control Signals" let me conclude that clock-enable is not simple synchronus clear signal for clock. it is not similar to sclr for data-in port of flip-flop.

So I see inconsistent in text and figures. And no any explanation at all. Use it "as is", dear engineer xD

Okay I found where I've read about gating ... it is "Quartus Handbook Volume 2 : Design Implementation and Optimization", Chapter 13. Power Optimization, paragraph Clock Power Management.

But as usual no any information how control signals should be related to clock. I mean when to assert or to deassert.

i don't think that it will be good practice to update control signals on the same active-edge of running clock, without any shifting them in phase.

then what is the minimal shift for phase?

Are you talking about signals in your synchronous design, or asynchronous load/clear?

Synchronous control signals in your design should always be updated on the rising edge of the same clock.

Asynchronous control signals (ie. load/reset) should be released synchronous to the clock.

This is from the Arria V and Cyclone V design Guidelines:

--- Quote Start ---

&#9632; If the clock signal is not available when reset is asserted, an asynchronous reset is

typically used to reset the logic.

&#9632; The recommended reset architecture allows the reset signal to be asserted

asynchronously and deasserted synchronously.

&#9632; The source of the reset signal is connected to the asynchronous port of the registers,

which can be directly connected to global routing resources.

&#9632; The synchronous deassertion allows all state machines and registers to start at the

same time.

&#9632; Synchronous deassertion avoids an asynchronous reset signal from being released

at, or near, the active clock edge of a flipflop that can cause the output of the flipflop

to go to a metastable unknown state.

For more information about good reset design, refer to industry papers such as the

analysis of reset architecture at www.sunburst-design.com/papers (http://www.sunburst-design.com/papers).

--- Quote End ---

https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/an/an662.pdf

Nice, i've read it before.

I want to say that the situation might exists when synchronous control signal deasserted before active edge of clock

So control signal should be deasserted after clock-transition. does it take place naturally only on tPD or some care need???

fast control signal and slow clock situation.

A synchronous control signal cannot be deasserted before the active edge of a clock - It can only change after an edge - otherwise it's not a synchronous control signal.

Its the edge that causes the transition. If it was to change before an edge it would have violated the hold time. This will be analysed by timequest.

Okay. get it.

But i still tend for : even control signals changed witch clock with the same frequency as data clock. does phase shift possible between these two clocks to improve hold time or it doesn't need??? for example when you try use control signal with 180 degree phase shift <- you might get setup violation.

I ask cause ICG (iternal clock gate) is generated per LAB at this labclkena signal. and I feel weak analysis for the topic.

Frequency Contol signal clock = Frequency data signal, Control signal clock has phase shift to data signal clock.

As a rule - keep everything on the same clock. Dont mess about with different phases.

If you need to cross a clock domain then use safe methods (dual port ram, fifo etc)

Why are you generating different phases of the clock?

cause i try understand this LAB-wide clock-enable. Must i take care or not.

okay how long sload or sclr signal should be holded so all register involved in update get proper new values.

and perhaps compensate timing when new value for control signal should be provided. so the new value for control signal is a little bit late arriving )

Will the result of timequest analysis be changed? if T is period for clock, what will be if control signal will be updated on new clock delayed for T/64, T/32 and so on.

Okay let it be a research work for others.