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Altera_Forum
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10 years ago

Question about Clock Enable port on D flip flop

I am using clock enable signal to synchronize my VHDL design with an external software. Here is how one of the flipflops look like in RTL viewer http://www.alteraforum.com/forum/attachment.php?att...
Altera_Forum's avatar
Altera_Forum
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10 years ago

As a rule - keep everything on the same clock. Dont mess about with different phases.

If you need to cross a clock domain then use safe methods (dual port ram, fifo etc)

Why are you generating different phases of the clock?