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Altera_Forum
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10 years ago

Question about Clock Enable port on D flip flop

I am using clock enable signal to synchronize my VHDL design with an external software. Here is how one of the flipflops look like in RTL viewer http://www.alteraforum.com/forum/attachment.php?att...
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Altera_Forum
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10 years ago

Nice, i've read it before.

I want to say that the situation might exists when synchronous control signal deasserted before active edge of clock

So control signal should be deasserted after clock-transition. does it take place naturally only on tPD or some care need???

fast control signal and slow clock situation.