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Altera_Forum
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10 years ago

Question about Clock Enable port on D flip flop

I am using clock enable signal to synchronize my VHDL design with an external software. Here is how one of the flipflops look like in RTL viewer http://www.alteraforum.com/forum/attachment.php?att...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

cause i try understand this LAB-wide clock-enable. Must i take care or not.

okay how long sload or sclr signal should be holded so all register involved in update get proper new values.

and perhaps compensate timing when new value for control signal should be provided. so the new value for control signal is a little bit late arriving )

Will the result of timequest analysis be changed? if T is period for clock, what will be if control signal will be updated on new clock delayed for T/64, T/32 and so on.

Okay let it be a research work for others.