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Honored Contributor
Honored ContributorQuestion about Clock Enable port on D flip flop
I am using clock enable signal to synchronize my VHDL design with an external software. Here is how one of the flipflops look like in RTL viewer http://www.alteraforum.com/forum/attachment.php?att...
Altera_ForumHonored Contributor
Honored ContributorI think it is like clock gating at source but per LAB module so you have incoming clock in flip-flop that was gated <-it is what I achieve from reading handbook for Cyclone V. But how will be right? from documentaion it is not really clear.
And it should be an issue for those who writes such bad technical papers 'you have two clocks and three clock-enable', very short explanation. where is third clock? Really bad clarification in docs for architecture of ALM and LAB in Cyclone V handbook found at web site. The docs for MAX10 in this case better. but who know except those who develope it?
