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Altera_Forum
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10 years ago

Question about Clock Enable port on D flip flop

I am using clock enable signal to synchronize my VHDL design with an external software. Here is how one of the flipflops look like in RTL viewer http://www.alteraforum.com/forum/attachment.php?att...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

) I know that it is not shown at figures but last sentence in pargraph " LAB Control Signals" let me conclude that clock-enable is not simple synchronus clear signal for clock. it is not similar to sclr for data-in port of flip-flop.

So I see inconsistent in text and figures. And no any explanation at all. Use it "as is", dear engineer xD