Honored Contributor
Honored ContributorAre you talking about signals in your synchronous design, or asynchronous load/clear?
Synchronous control signals in your design should always be updated on the rising edge of the same clock. Asynchronous control signals (ie. load/reset) should be released synchronous to the clock. This is from the Arria V and Cyclone V design Guidelines: --- Quote Start --- ■ If the clock signal is not available when reset is asserted, an asynchronous reset is typically used to reset the logic. ■ The recommended reset architecture allows the reset signal to be asserted asynchronously and deasserted synchronously. ■ The source of the reset signal is connected to the asynchronous port of the registers, which can be directly connected to global routing resources. ■ The synchronous deassertion allows all state machines and registers to start at the same time. ■ Synchronous deassertion avoids an asynchronous reset signal from being released at, or near, the active clock edge of a flipflop that can cause the output of the flipflop to go to a metastable unknown state. For more information about good reset design, refer to industry papers such as the analysis of reset architecture at www.sunburst-design.com/papers (http://www.sunburst-design.com/papers). --- Quote End --- https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/an/an662.pdf
