Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Question about Clock Enable port on D flip flop

I am using clock enable signal to synchronize my VHDL design with an external software. Here is how one of the flipflops look like in RTL viewer http://www.alteraforum.com/forum/attachment.php?att...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

A synchronous control signal cannot be deasserted before the active edge of a clock - It can only change after an edge - otherwise it's not a synchronous control signal.

Its the edge that causes the transition. If it was to change before an edge it would have violated the hold time. This will be analysed by timequest.