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Honored Contributor
Honored ContributorQuestion about Clock Enable port on D flip flop
I am using clock enable signal to synchronize my VHDL design with an external software. Here is how one of the flipflops look like in RTL viewer http://www.alteraforum.com/forum/attachment.php?att...
Altera_ForumHonored Contributor
Honored ContributorOkay I found where I've read about gating ... it is "Quartus Handbook Volume 2 : Design Implementation and Optimization", Chapter 13. Power Optimization, paragraph Clock Power Management.
But as usual no any information how control signals should be related to clock. I mean when to assert or to deassert. i don't think that it will be good practice to update control signals on the same active-edge of running clock, without any shifting them in phase.then what is the minimal shift for phase?
