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Honored Contributor
Honored ContributorQuestion about Clock Enable port on D flip flop
I am using clock enable signal to synchronize my VHDL design with an external software. Here is how one of the flipflops look like in RTL viewer http://www.alteraforum.com/forum/attachment.php?att...
Altera_ForumHonored Contributor
Honored ContributorIt is there, it is just not shown in the diagram (no clock gating at all as suggested by alex96)
Page 1-5 from https://www.altera.com/en_us/pdfs/literature/hb/cyclone-v/cv_5v2.pdf "GPIO pins or internal logic drives the clock enable signal."
