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Honored ContributorQuartus can't fit small design on large FPGA
Hey All!
I'm having an issue trying to synthesize and perform timing analysis on a 8 line sorting network. The good news is that I've implemented it with just combinational logic and run a timing simulation in ModelSim for a Cyclone device. The bad news starts now that I need to know the timing for a Stratix V, for which timing simulation is not supported. So I looked into TimeQuest, but it appears to need clocks in order to make constraints for the rest of the design. I think no problem, I'll just make the first stage synchronous by adding a clocked process. But there is a problem, now this little design doesn't want to fit on the huge FPGA. Here's the code, hopefully its formatted correctly. Thanks in advance for any insights!!
library IEEE;
use IEEE.std_logic_1164.all;
entity sort is -- Sorting Network
port ( clk : in std_logic;
rst : in std_logic;
load : in std_logic;
in1 : in std_logic_vector(7 downto 0);
in2 : in std_logic_vector(7 downto 0);
in3 : in std_logic_vector(7 downto 0);
in4 : in std_logic_vector(7 downto 0);
in5 : in std_logic_vector(7 downto 0);
in6 : in std_logic_vector(7 downto 0);
in7 : in std_logic_vector(7 downto 0);
in8 : in std_logic_vector(7 downto 0);
out1 : out std_logic_vector(7 downto 0);
out2 : out std_logic_vector(7 downto 0);
out3 : out std_logic_vector(7 downto 0);
out4 : out std_logic_vector(7 downto 0);
out5 : out std_logic_vector(7 downto 0);
out6 : out std_logic_vector(7 downto 0);
out7 : out std_logic_vector(7 downto 0);
out8 : out std_logic_vector(7 downto 0));
end sort;
architecture behavioral of sort is
type book is array (0 to 7) of std_logic_vector(7 downto 0); -- first define the type of array.
signal bid_book : book; --bid_book is a 16 element array of integers.
signal offer_book : book; --bid_book is a 16 element array of integers.
signal match_vec : std_logic_vector(7 downto 0);
signal market_vec : std_logic_vector(7 downto 0); -- lowest price in offer book
-- Comparator Signals
signal stage1,stage2,stage3,stage4,stage5,stage6 : book;
begin -- circuits of Sm
process(clk,rst)
begin
if(rst = '1') then
offer_book(0) <= "00000000";
offer_book(1) <= "00000000";
offer_book(2) <= "00000000";
offer_book(3) <= "00000000";
offer_book(4) <= "00000000";
offer_book(5) <= "00000000";
offer_book(6) <= "00000000";
offer_book(7) <= "00000000";
elsif rising_edge(clk) then
-- if load = '1' then
offer_book(0) <= in1;
offer_book(1) <= in2;
offer_book(2) <= in3;
offer_book(3) <= in4;
offer_book(4) <= in5;
offer_book(5) <= in6;
offer_book(6) <= in7;
offer_book(7) <= in8;
-- end if;
end if;
end process;
-- Sorting Network Stage 1 - 4 comparators
stage1(0) <= offer_book(0) when offer_book(0) < offer_book(1) else offer_book(1);
stage1(1) <= offer_book(1) when offer_book(0) < offer_book(1) else offer_book(0);
stage1(2) <= offer_book(2) when offer_book(2) < offer_book(3) else offer_book(3);
stage1(3) <= offer_book(3) when offer_book(2) < offer_book(3) else offer_book(2);
stage1(4) <= offer_book(4) when offer_book(4) < offer_book(5) else offer_book(5);
stage1(5) <= offer_book(5) when offer_book(4) < offer_book(5) else offer_book(4);
stage1(6) <= offer_book(6) when offer_book(6) < offer_book(7) else offer_book(7);
stage1(7) <= offer_book(7) when offer_book(6) < offer_book(7) else offer_book(6);
-- Sorting Network Stage 2 - 4 comparators
stage2(0) <= stage1(0) when stage1(0) < stage1(2) else stage1(2);
stage2(1) <= stage1(1) when stage1(1) < stage1(3) else stage1(3);
stage2(2) <= stage1(2) when stage1(0) < stage1(2) else stage1(0);
stage2(3) <= stage1(3) when stage1(1) < stage1(3) else stage1(1);
stage2(4) <= stage1(4) when stage1(4) < stage1(6) else stage1(6);
stage2(5) <= stage1(5) when stage1(5) < stage1(7) else stage1(7);
stage2(6) <= stage1(6) when stage1(4) < stage1(6) else stage1(4);
stage2(7) <= stage1(7) when stage1(5) < stage1(7) else stage1(5);
-- Sorting Network Stage 3 - 2 comparators
stage3(0) <= stage2(0);
stage3(1) <= stage2(1) when stage2(1) < stage2(2) else stage2(2);
stage3(2) <= stage2(2) when stage2(1) < stage2(2) else stage2(1);
stage3(3) <= stage2(3);
stage3(4) <= stage2(4);
stage3(5) <= stage2(5) when stage2(5) < stage2(6) else stage2(6);
stage3(6) <= stage2(6) when stage2(5) < stage2(6) else stage2(5);
stage3(7) <= stage2(7);
-- Sorting Network Stage 4 - 4 comparators
stage4(0) <= stage3(0) when stage3(0) < stage3(4) else stage3(4);
stage4(1) <= stage3(1) when stage3(1) < stage3(5) else stage3(5);
stage4(2) <= stage3(2) when stage3(2) < stage3(6) else stage3(6);
stage4(3) <= stage3(3) when stage3(3) < stage3(7) else stage3(7);
stage4(4) <= stage3(4) when stage3(0) < stage3(4) else stage3(0);
stage4(5) <= stage3(5) when stage3(1) < stage3(5) else stage3(1);
stage4(6) <= stage3(6) when stage3(2) < stage3(6) else stage3(2);
stage4(7) <= stage3(7) when stage3(3) < stage3(7) else stage3(3);
-- Sorting Network Stage 5 - 2 comparators
stage5(0) <= stage4(0);
stage5(1) <= stage4(1);
stage5(2) <= stage4(2) when stage4(2) < stage4(4) else stage4(4);
stage5(3) <= stage4(3) when stage4(3) < stage4(5) else stage4(5);
stage5(4) <= stage4(4) when stage4(2) < stage4(4) else stage4(2);
stage5(5) <= stage4(5) when stage4(3) < stage4(5) else stage4(3);
stage5(6) <= stage4(6);
stage5(7) <= stage4(7);
-- Sorting Network Stage 6 - 3 comparators
out1 <= stage5(0);
out2 <= stage5(1) when stage5(1) < stage5(2) else stage5(2);
out3 <= stage5(2) when stage5(1) < stage5(2) else stage5(1);
out4 <= stage5(3) when stage5(3) < stage5(4) else stage5(4);
out5 <= stage5(4) when stage5(3) < stage5(4) else stage5(3);
out6 <= stage5(5) when stage5(5) < stage5(6) else stage5(6);
out7 <= stage5(6) when stage5(5) < stage5(6) else stage5(5);
out8 <= stage5(7);
end behavioral; -- of Sm
