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Altera_Forum
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13 years ago

Quartus can't fit small design on large FPGA

Hey All! I'm having an issue trying to synthesize and perform timing analysis on a 8 line sorting network. The good news is that I've implemented it with just combinational logic and run a tim...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Ah, I hope this is the solution! I don't have my dev board yet so I didn't see a real need to assign any pins. Thanks for the help! :)