CXL Type 2 DMA/Mem Access Triggers CPU MCE on Sapphire Rapids

We are using an Intel DK-DEV-AGI027-RA-B board (programmed with CXL Type 2 IP) on a 2-socket Intel Xeon Platinum 8468V (Sapphire Rapids) platform. The card is in socket 1, behind root port 0000:a7:01.0 (8086:352a) and CXL host bridge ACPI0016:07, and is enumerated as 0000:a8:00.0 / 0000:a8:00.1. When I simultaneously access the Type 2 device memory and cause the device to access host memory via DMA, the host logs a CPU2 “uncorrectable machine check exception” and hangs. The fault record contains only the CPU-side IEH (8086:0b23, BDF a7:00.4) and one PCIe:(0XA7:0X00.0X04) record. There is no OS AER event because AER is firmware-first (OsNativeAerSupport is disabled). The boot console also shows “Cannot find PCIe Capability in CXL 1.1 upstream RCRB, cannot set ASPM” and the repeated message “LocateExtCapability () Incorrect DS link encountered on A800FFC pci config space.” Could you please advise why this occurs and how to decode the IEH/eMCA records and capture the exact AER TLP type (config vs MMIO vs CXL.cache/DMA)?