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Occasional ContributorA5E(B) EMIF : LPDDR4 minimum memory clock
I find plenty of maximum clock specs for the EMIF. But I want to know minimum clock .
slowing the clock down can save quite alot of power.
The EMIF wizard configurator lists :(External Memory Interfaces (EMIF) IP User Guide)
LPDDR4 : "Legal values are: 800, 1066.667, 1333.333, 1600, 1866.667, 2133.333"
but the PTA permits entries down to 625 MHz.....
But I would like to operate the interface at 200 or 400 MHz, at times....
(1) Putting aside the presets in the tools , what is minimum clock that the EMIF can run at ?
(2) Are there asynchronous paths that if the clock is too slow will be violated ?
(3) Many memory timing constants are multiples of the clock, and we accept that the config range may not be available for slow clocks. We also accept there may be maximum AXI interface clock to memory clock ratios.
In Xilinx MPSoC , you can run it down to 100 MHz... Saves a ton of power.
Most LPDDR4 is specified down to 10 MHz clock ... with only a few clock cycle latency (because that's in fixed internal time)
Regards, Glen. (evaluating moving products to Altera from Xilinx) .
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