Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Quartus can't fit small design on large FPGA

Hey All! I'm having an issue trying to synthesize and perform timing analysis on a 8 line sorting network. The good news is that I've implemented it with just combinational logic and run a tim...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Hi,

I had a similar issue with the Stratix V and Q11.1SP2.

A very simple design was synthesized in 5 sec, and 35 minutes later, there was an error saying the design could not fit.

I opened a SR and the altera support reported that there was a bug in the prefitter. The solution was to assign the pin of the clock signal.

You can try this and relaunch the compilation.

Since I started my Stratix V design, I really have many headaches with Q11 and now Q12.