Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Quartus can't fit small design on large FPGA

Hey All! I'm having an issue trying to synthesize and perform timing analysis on a 8 line sorting network. The good news is that I've implemented it with just combinational logic and run a tim...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

It fits! I appears that I had an issue with my sdc file that I created when I was going through a tutorial. I fixed that, and it looks like I'm good to go!

Thanks everyone!