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Honored Contributor
Honored ContributorQuartus can't fit small design on large FPGA
Hey All! I'm having an issue trying to synthesize and perform timing analysis on a 8 line sorting network. The good news is that I've implemented it with just combinational logic and run a tim...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Hey All! ... So I looked into TimeQuest, but it appears to need clocks in order to make constraints for the rest of the design. I think no problem, I'll just make the first stage synchronous by adding a clocked process. ... --- Quote End --- Using Timequest properly assumes that you provide a sdc-file in which you define the timing constraints. Most import is the clock frequency. It is set per default to 1000MHz, which is rather high. You can observe the recognized clocks in the Timequest GUI by clicking Diagnostics -> Report Clocks Defining your own clock (50MHz for example) in a sdc-file:
create_clock -add -period 20.000 -waveform { 0.000 10.000 } -name think_of_a_pretty_clock_name 
