Quartus can't fit small design on large FPGA

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It fits! I appears that I had an issue with my sdc file that I created when I was going through a tutorial. I fixed that, and it looks like I'm good to go!

Thanks everyone!

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Congratulations!

NB: If you use a PLL in your design you'll have simply to add

derive_pll_clocks

to your sdc-file after you define the clock mentioned earlier.

Note that QuartusII treat all clocks as related clocks by default.

That means that if you've clocks in you design that can't be expressed as clock1=n*clock2 where n is an integer and there are paths between these clocks, the Quartus-Fitter will not be able to fit them (no fitter would). This will keep of the fitter to focus on the *really* critical paths. You'll have to treat these "unrelated/asynchronous" clocks in different clock groups like:

set_clock_groups -asynchronous 
-group { 
   {think_of_a_pretty_clock_name} 
       } 
-group { 
   {clock2_as_seen_in_TIMEQUEST_NAME_FINDER} 
       }

Regardless wether constraints you'll use; you'll have to write HDL-code that treats these unrelated clock paths properly.

To observe if paths exits between (unrelated) clocks open the Timequest GUI and click

Diagnostics -> Report Clock Transfers