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Honored Contributor
Honored ContributorQuartus can't fit small design on large FPGA
Hey All! I'm having an issue trying to synthesize and perform timing analysis on a 8 line sorting network. The good news is that I've implemented it with just combinational logic and run a tim...
Altera_ForumHonored Contributor
Honored ContributorWhat is the problem reported ? Could you post the message ?
