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Altera_Forum
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13 years ago

Quartus can't fit small design on large FPGA

Hey All! I'm having an issue trying to synthesize and perform timing analysis on a 8 line sorting network. The good news is that I've implemented it with just combinational logic and run a tim...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Thanks for the tip jb123. That's one step past where I am, but it'll help when I get there.

Assigning the clock pin did not fix the problem. I created a top level entity with only a clock and reset pin which instantiates my sorter. I assigned those pins, and it still doesn't fit, so I guess I'll open an SR.