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Altera_Forum's avatar
Altera_Forum
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9 years ago

Power on detection

Hello, please help me solving the issue.

I have FPGA (cyclone-3 based) module connected to another system. That system generates reset signal on power on, and FPGA translates this signal to its devices. But it did not work some times, and I found out why: when power is applied, system activates reset signal, at the same time FPGA starts configuration from EPCS device. However, it seems configuration takes longer than system has reset signal active, and when FPGA is "ready" reset time has already finished, and devices attached to FPGA were not reset properly ("reset" output pin of FPGA was tri-stated during config).

Of course there's option to solve it in hardware - put pull-down resistor onto FPGA "reset" output pin, and during configuration all devices will be in reset state.

Is there any way to solve this issue in FPGA configuration - e.g. detect the end of configuration so that FPGA can perform reset to its attached devices?

Please advise. Thank you!

12 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    well, not sure if this is what you are after, nut you could bring an output pin on the fpga active for an x ammount of time and then deactivate it and use that for the device reset.

  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    Have the system that is connected to the FPGA board hold the reset signal on long enough for the FPGA to finish configuration and the attached devices to reset themselves.

  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    @PietervanderStar: hardware design was already done, and devices are assembled.

    @Galfonz: I think you described the issue which I need to solve. It does not hold reset required time, and it is an issue. It can not be changed.

    I am looking to the solution which can be put into FPGA config - for example, some internal input/register that indicates that configuration just finished, which I can reset after performing afterconfig actions.
  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    So you have assembled hardware, an unchangable design for your FPGA and you want to change system behaviour?

    Other than what was said before I don't really see an option.
  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    --- Quote Start ---

    So you have assembled hardware, an unchangable design for your FPGA and you want to change system behaviour?

    --- Quote End ---

    Why not? It is FPGA.

    --- Quote Start ---

    Other than what was said before I don't really see an option.

    --- Quote End ---

    http://www.alteraforum.com/forum/showthread.php?t=6602 - setting initial values of the register. It gives good overview on the subject, but does not IMHO provide soltuons to possible metastability/register operational time violation if configuration ends/operation starts on the external clock transition.

    I found out that I just need internal reset controller.

    Edit: http://japan.xilinx.com/support/documentation/white_papers/wp272.pdf see page 5 circuit diagram at the bottom making reset signal synchronous.
  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    Well to the first:

    --- Quote Start ---

    well, not sure if this is what you are after, nut you could bring an output pin on the fpga active for an x ammount of time and then deactivate it and use that for the device reset.

    --- Quote End ---

    --- Quote Start ---

    @PietervanderStar: hardware design was already done,

    --- Quote End ---

    This is along the lines I was thinking.

    --- Quote Start ---

    setting initial values of the register.

    --- Quote End ---

    And after x ammount of time changing that value.

    For the second, you could read this (http://www.alteraforum.com/forum/showthread.php?t=45135&highlight=reset+synchroniser) thread.
  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    --- Quote Start ---

    And after x ammount of time changing that value.

    --- Quote End ---

    It would be ideal solution if one possible condition. Imagine, as proposed in that thread, I set up initial counter to be 0, and clock is running asynchronously. If all bits of register setup, from X to 0, will happen on the rising edge of the clock of counter (reg[..]<=reg[...]+1) it is big question which value reg[...] will get. I assume all bits in reg[...] are affected by it, not just bit 0 as assumed here http://www.alteraforum.com/forum/showthread.php?t=6602&page=3&p=27012#post27012.
  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    The clock is synchronous as that is the thing the system runs on.

    If you add '1' to a vector potentially the entire vector is affected (carries).

    concerning the power-up values, I have never had a problem with them, but to be fair, I have never really had them in a critical position. I use them for counter inits, and I have never found them to be off.

    But I cannot really say anything about that.
  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    --- Quote Start ---

    The clock is synchronous as that is the thing the system runs on.

    --- Quote End ---

    Not sure I agree with you on this. To my understanding configuration is performed using some internal clock, however all logic is being controlled by another, external clock. As they are not correlated, they are asynchronous. Even worse, I did not see the possibility to source this "config clock" in user mode.
  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    I did some testing, and it seems output pin under consideration is powered up high and remains high during configuration.

    This is pin 11, "IO/DIFFIO_L4n". This output pin is only connected to the input of another chip, and there's no pull-up resistor on the line - even internal to the "recipient" chip. Within configuration this output pin is "direct connection" to another FPGA's input pin, which is low at power up, and remains low for some time (reset signal).

    Any comment? Manual https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/an/an466.pdf page 22 table 6 states "output buffers tri-stated", but I clearly see with logic probe it gives high onto the line until FPGA completes configuration.