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Altera_Forum's avatar
Altera_Forum
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10 years ago

Power on detection

Hello, please help me solving the issue. I have FPGA (cyclone-3 based) module connected to another system. That system generates reset signal on power on, and FPGA translates this signal to its...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

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The clock is synchronous as that is the thing the system runs on.

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Not sure I agree with you on this. To my understanding configuration is performed using some internal clock, however all logic is being controlled by another, external clock. As they are not correlated, they are asynchronous. Even worse, I did not see the possibility to source this "config clock" in user mode.