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And after x ammount of time changing that value.
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It would be ideal solution if one possible condition. Imagine, as proposed in that thread, I set up initial counter to be 0, and clock is running asynchronously. If all bits of register setup, from X to 0, will happen on the rising edge of the clock of counter (reg[..]<=reg[...]+1) it is big question which value reg[...] will get. I assume all bits in reg[...] are affected by it, not just bit 0 as assumed here
http://www.alteraforum.com/forum/showthread.php?t=6602&page=3&p=27012#post27012.
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