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Altera_Forum
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9 years ago

Power on detection

Hello, please help me solving the issue. I have FPGA (cyclone-3 based) module connected to another system. That system generates reset signal on power on, and FPGA translates this signal to its...
Altera_Forum's avatar
Altera_Forum
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9 years ago

I did some testing, and it seems output pin under consideration is powered up high and remains high during configuration.

This is pin 11, "IO/DIFFIO_L4n". This output pin is only connected to the input of another chip, and there's no pull-up resistor on the line - even internal to the "recipient" chip. Within configuration this output pin is "direct connection" to another FPGA's input pin, which is low at power up, and remains low for some time (reset signal).

Any comment? Manual https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/an/an466.pdf page 22 table 6 states "output buffers tri-stated", but I clearly see with logic probe it gives high onto the line until FPGA completes configuration.