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So you have assembled hardware, an unchangable design for your FPGA and you want to change system behaviour?
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Why not? It is FPGA.
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Other than what was said before I don't really see an option.
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http://www.alteraforum.com/forum/showthread.php?t=6602 - setting initial values of the register. It gives good overview on the subject, but does not IMHO provide soltuons to possible metastability/register operational time violation if configuration ends/operation starts on the external clock transition.
I found out that I just need internal reset controller.
Edit:
http://japan.xilinx.com/support/documentation/white_papers/wp272.pdf see page 5 circuit diagram at the bottom making reset signal synchronous.
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