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Altera_Forum's avatar
Altera_Forum
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10 years ago

Power on detection

Hello, please help me solving the issue. I have FPGA (cyclone-3 based) module connected to another system. That system generates reset signal on power on, and FPGA translates this signal to its...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

@PietervanderStar: hardware design was already done, and devices are assembled.

@Galfonz: I think you described the issue which I need to solve. It does not hold reset required time, and it is an issue. It can not be changed.

I am looking to the solution which can be put into FPGA config - for example, some internal input/register that indicates that configuration just finished, which I can reset after performing afterconfig actions.