Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Power on detection

Hello, please help me solving the issue. I have FPGA (cyclone-3 based) module connected to another system. That system generates reset signal on power on, and FPGA translates this signal to its...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

The clock is synchronous as that is the thing the system runs on.

If you add '1' to a vector potentially the entire vector is affected (carries).

concerning the power-up values, I have never had a problem with them, but to be fair, I have never really had them in a critical position. I use them for counter inits, and I have never found them to be off.

But I cannot really say anything about that.