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Altera_Forum
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9 years ago

Power on detection

Hello, please help me solving the issue. I have FPGA (cyclone-3 based) module connected to another system. That system generates reset signal on power on, and FPGA translates this signal to its...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Well to the first:

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well, not sure if this is what you are after, nut you could bring an output pin on the fpga active for an x ammount of time and then deactivate it and use that for the device reset.

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@PietervanderStar: hardware design was already done,

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This is along the lines I was thinking.

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setting initial values of the register.

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And after x ammount of time changing that value.

For the second, you could read this (http://www.alteraforum.com/forum/showthread.php?t=45135&highlight=reset+synchroniser) thread.