p0_pin_perst_n remains asserted when implementing GTS AXI Streaming intel FPGA IP for PCI Express

Hi Chester,

May I know if you have any updates?

Thanks.

Best Regards,

Ven

Hi Chester,

I am sorry for the late reply.

Thank you for the updates.

Since you are using Agilex™ 5 ES E-Series devices, please make sure the pin location assignment for p0_pin_perst_n_i and p0_pin_perst_n_1_i are assigned correctly. For the other reset pin that is not used as PERST#, it must be left floating at board level. Please refer to Section 4.2 of the user guide: https://www.intel.com/content/www/us/en/docs/programmable/813754/25-1/resets-18963.html

After rebooting the PC, the PERST# signal should toggle if the pin assignment is correct. Since PERST# is controlled by the host system, it is important to confirm that the issue is not related to the PC itself.

Could you please try the following:

• Use a different PCIe slot in your current PC, if available.
• Test the board in another PC, if possible.
• If you have another FPGA card, check whether it toggles PERST# correctly in the same slot.

Thanks.

Best Regards,

Ven

Hi Chester,

My apologies for the late reply.

Please allow me some time to check the documents you shared.

Would you be able to run the test on another PC to verify whether the issue is dependent on the PC? Is the board powered by the PC?

Kindly take note that Sep 5 is a national holiday, please expect a delay in response. I will get back to you next week.

Thanks.

Best Regards,

Ven

Hi Chester,

I could not view the full signals from the attached image (2025-08-18_103808_129.png).

Could you please follow these steps to capture the signals? Please use the Design Example generated from Quartus without modifying the design (only add STP and pin assignments for the Eagle board):

1.Power on the PC (the board powers on at the same time).

2. Program the .sof file.

3.Start capturing the Transitional Signal Tap instance (click Run Analysis).

4.Reboot the PC.

5.When the PC is up, stop the Signal Tap capture (click Stop Analysis).

Please make sure the pin assignments for refclk and PERST# are correct.

Have you ever observed p0_pin_perst_n toggling from low to high?

Thanks.

Best Regards,

Ven

Hi Chester,

Thank you for providing the updates, and my apologies for the late reply.

5. I didn't Insert the PCIe board into the motherboard everytime when testing.

Could you clarify this? My understanding is that the PCIe board (Arrow Eagle board) is always inserted into the motherboard, and you test by programming the SOF and rebooting the PC.

6. The pin p0_pin_perst_n is low and LTSSM stuck on state 0 , is that normal ? I tried to capture the STP using Type: Transitional in the storage qualifier settings but it didn't work .

No, p0_pin_perst_n should toggle from low to high, and then LTSSM should eventually reach h11 (L0 state). You can capture this using STP with Transitional settings. What are the errors you encountered when setting the storage qualifier to Transitional?

Thanks.

Best Regards,

Ven

Hi Chester,

Good day.

Could you please get back to us on the previous message?

Thanks.

Best Regards,

Ven

Hi Chester,

Thanks for reaching out.

Could you please address the following items?

1. May I know what board/dev kit you use?
2. Could you confirm the pin assignments are correct?
3. Could you try to use the PIO Design Example generated directly from Quartus?
4. Have you tried to bring up the PCIe using the same design example in the previous Quartus versions?
5. What is the hardware setup and the procedures you performed to capture the STP? Have you rebooted the workstation/PC after programming the SOF?
6. From the STP you shared, the PCIe IP is out of reset. Could you capture the STP using Type: Transitional in the storage qualifier settings?

Thanks.

Best Regards,

Ven