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ZChester's avatar
ZChester
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4 months ago

p0_pin_perst_n remains asserted when implementing GTS AXI Streaming intel FPGA IP for PCI Express

Hi, I'm using GTS AXI Streaming intel FPGA IP for PCI Express to implement PCIe on Agilex 5 FPGA (A5ED065BB32AE4 ,Quartus Prime 25.1) . I connect Pin p0_pin_perst_n_i to a 3.3v pll up resistance on ...
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VenT_Altera's avatar
VenT_Altera
Icon for Frequent Contributor rankFrequent Contributor
3 months ago

Hi Chester,


My apologies for the late reply.

Please allow me some time to check the documents you shared.


Would you be able to run the test on another PC to verify whether the issue is dependent on the PC? Is the board powered by the PC?


Kindly take note that Sep 5 is a national holiday, please expect a delay in response. I will get back to you next week.


Thanks.

Best Regards,

Ven


ZChester's avatar
ZChester
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3 months ago

Hi Ven,

I tried to run the test on both of my PC and another PC in two different ways . One is program Agilex5 with the .sof file while the fpga is powered by its power adapter and it remains on during the restart process of PC . Another is program Agilex5 with the .jic file and let the PC power on the board when the PC restart .Still cannot observe p0_pin_perst_n toggling from low to high .

Wish you have a good holiday .

Best Regards ,

Chester