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ZChester's avatar
ZChester
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4 months ago

p0_pin_perst_n remains asserted when implementing GTS AXI Streaming intel FPGA IP for PCI Express

Hi, I'm using GTS AXI Streaming intel FPGA IP for PCI Express to implement PCIe on Agilex 5 FPGA (A5ED065BB32AE4 ,Quartus Prime 25.1) . I connect Pin p0_pin_perst_n_i to a 3.3v pll up resistance on ...
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VenT_Altera's avatar
VenT_Altera
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3 months ago

Hi Chester,


May I know if you have any updates?


Thanks.

Best Regards,

Ven


ZChester's avatar
ZChester
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3 months ago

Hi Ven,

Sorry for getting back to you late .

I tried an example design generated by Quartus 24.2 . The example design could work correctly now when i test it on Quartus 24.2 . It seems like the problem is not about PCIe slot or PC .

Best Regards ,

Chester