p0_pin_perst_n remains asserted when implementing GTS AXI Streaming intel FPGA IP for PCI Express

Hi Ven,

I found a new problem . When i execute a write read test using the linux driver which is generated together with the example design , every read back data is 0x00000000 . Also , the WinDriver software could not detect a bar memory . I set the BAR0 size to 4MB when i generated the ed .

I also tried to use the SSGDMA IP together with the PCIe ip in my own design. when i set BAR0 to a 4KB prefetchable memory , i can write and read registers through the WinDriver , but i can't observe the axi st_rx_valid toggle high. The BAR0 memory is supposed to be in the SSGDMA and is read or written through axi-stream ports connected to the PCIe IP . What's more , i don't see the axi-lite awaddr_ready toggle high when SSGDMA try to write PCIe IP's csr registers .

Best Regards ,

Chester