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ZChester's avatar
ZChester
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4 months ago

p0_pin_perst_n remains asserted when implementing GTS AXI Streaming intel FPGA IP for PCI Express

Hi, I'm using GTS AXI Streaming intel FPGA IP for PCI Express to implement PCIe on Agilex 5 FPGA (A5ED065BB32AE4 ,Quartus Prime 25.1) . I connect Pin p0_pin_perst_n_i to a 3.3v pll up resistance on ...
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VenT_Altera's avatar
VenT_Altera
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4 months ago

Hi Chester,


I could not view the full signals from the attached image (2025-08-18_103808_129.png).

Could you please follow these steps to capture the signals? Please use the Design Example generated from Quartus without modifying the design (only add STP and pin assignments for the Eagle board):


1.Power on the PC (the board powers on at the same time).

2. Program the .sof file.

3.Start capturing the Transitional Signal Tap instance (click Run Analysis).

4.Reboot the PC.

5.When the PC is up, stop the Signal Tap capture (click Stop Analysis).


Please make sure the pin assignments for refclk and PERST# are correct.

Have you ever observed p0_pin_perst_n toggling from low to high?


Thanks.

Best Regards,

Ven


ZChester's avatar
ZChester
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4 months ago

Hi Ven,

Thanks for your reply !

What else signals do you need to see to help me out ?

I use the Design Example generated from Quartus only with these modifications .

1. I change the frequency of IOPLL refclk from 100Mhz to 25Mhz .

2. I add STP and pin assignments for the Eagle board .

I followed your guide but i have never observed p0_pin_perst_n toggling from low to high still .

I checked the pin assignments for refclk and PERST# and found nothing wrong with them . I will post some parts of user guide of the Eagle board in the following pictures so you can help me check .

Best Regards,

Chester