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Chester's avatar
Chester
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1 year ago

p0_pin_perst_n remains asserted when implementing GTS AXI Streaming intel FPGA IP for PCI Express

Hi, I'm using GTS AXI Streaming intel FPGA IP for PCI Express to implement PCIe on Agilex 5 FPGA (A5ED065BB32AE4 ,Quartus Prime 25.1) . I connect Pin p0_pin_perst_n_i to a 3.3v pll up resistance on ...
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VenT_Altera's avatar
VenT_Altera
Icon for Frequent Contributor rankFrequent Contributor
11 months ago

Hi Chester,


I am sorry for the late reply.

Thank you for the updates.


Since you are using Agilex™ 5 ES E-Series devices, please make sure the pin location assignment for p0_pin_perst_n_i and p0_pin_perst_n_1_i are assigned correctly. For the other reset pin that is not used as PERST#, it must be left floating at board level. Please refer to Section 4.2 of the user guide: https://www.intel.com/content/www/us/en/docs/programmable/813754/25-1/resets-18963.html


After rebooting the PC, the PERST# signal should toggle if the pin assignment is correct. Since PERST# is controlled by the host system, it is important to confirm that the issue is not related to the PC itself.

Could you please try the following:

  • Use a different PCIe slot in your current PC, if available.
  • Test the board in another PC, if possible.
  • If you have another FPGA card, check whether it toggles PERST# correctly in the same slot.


Thanks.

Best Regards,

Ven