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ZChester's avatar
ZChester
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4 months ago

p0_pin_perst_n remains asserted when implementing GTS AXI Streaming intel FPGA IP for PCI Express

Hi, I'm using GTS AXI Streaming intel FPGA IP for PCI Express to implement PCIe on Agilex 5 FPGA (A5ED065BB32AE4 ,Quartus Prime 25.1) . I connect Pin p0_pin_perst_n_i to a 3.3v pll up resistance on ...
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VenT_Altera's avatar
VenT_Altera
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4 months ago

Hi Chester,


Thanks for reaching out.


Could you please address the following items?

  1. May I know what board/dev kit you use?
  2. Could you confirm the pin assignments are correct?
  3. Could you try to use the PIO Design Example generated directly from Quartus?
  4. Have you tried to bring up the PCIe using the same design example in the previous Quartus versions?
  5. What is the hardware setup and the procedures you performed to capture the STP? Have you rebooted the workstation/PC after programming the SOF?
  6. From the STP you shared, the PCIe IP is out of reset. Could you capture the STP using Type: Transitional in the storage qualifier settings?


Thanks.

Best Regards,

Ven


ZChester's avatar
ZChester
Icon for New Contributor rankNew Contributor
4 months ago

Hi Ven，

Thanks for your reply !

I'm sorry for getting back to you late .

1. The board i use is AXE5-Eagle made by Arrow , not a Intel dev kit .

2. I confirm the pin assignments are correct . I'll post some related parts of schematic diagram in the following pictures .

3. Now i'm using a PIO Design Example generated directly from Quartus . But the situation is just the same .

4. I've never tried to do that since there is no other version of Quartus installed on my PC .

5. I didn't Insert the PCIe board into the motherboard everytime when testing. But when i did that , i did reboot the PC after

programming the SOF .

6. The pin p0_pin_perst_n is low and LTSSM stuck on state 0 , is that normal ? I tried to capture the STP using Type: Transitional in the storage qualifier settings but it didn't work .

Best Regards,

Chester