Multiplexer Output Glitching

Now if you only have to consider one input changing at at time, your above design with the 'keep' attributes seems to work best without glitching as 't' works on the first tier while 's' decides on the second tier in the purposely designed 2-tier logic. We now have 3 times the same circuit. But in theory even the simple circuit which muxes two inputs onto one output could glitch when the output selection tuns off faster than the other selection turns on. So if we could force a 'delayed' turnoff we would be glitchfree by design. But here we depend on the physical process in the LUT. In the days of TTL logic we could select devices with a TpHL > TpLH. We could infer that the same may be true inside an FPGA, but this might just be wishful thinking. Maybe you could ask Altera about the LUT TpLH and TpHL of the device you are using?

    assign q = s & a 
                | s & b
                | !s & c
                | !s & d;

I don't see that equation glitching in my project. I compiled and simulated the project for different families and get different results in the gate level simulation (and that is not exactly the real world ...)

I couldn't keep from searching a bit deeper and went back to some 'old' textbooks.

 
 y = !s & a
   |  s & b
   |  a & b
   ;

 wire gab , gcd , gabcd,  hab, hcd , habcd , iab , icd , iabcd , rab , rcd/* synthesis keep*/ ;
 assign  gab = !s & a0 ;
 assign  hab =  s & b0 ;
 assign  iab = a0 & b0 ;
 assign  rab = gab | hab | iab ;
	
 assign  gcd = !s & c0 ;
 assign  hcd =  s & d0 ;
 assign  icd = c0 & d0 ;
 assign  rcd = gcd | hcd | icd ;
	
 assign  gabcd = !t & rab ;
 assign  habcd =  t & rcd ;
 assign  iabcd = rab & rcd ;
 assign  q0 = gabcd | habcd | iabcd ;

Hi Josyb,

    wire x,y /* synthesis keep */;
    assign x = (t) ? d : c;
    assign y = (t) ? b : a;
    assign q = (s) ? x : y;

That is the major problem with asynchronous logic and FPGAs: they are not made for each other. Almost all FPGAs are pure synchronous beasts. (Except Achronix and maybe some newer start-up).

assign x = (t) ? d : c;

  x = !t & c
    |  t & d
    ;

I think you are wrong but please don't take that the wrong way, I'm not 100% sure that I'm right and would like to discuss this until we are both happy that we understand what is going on. Please rip anything I say to shreds so we can get to the bottom of it and both learn.

c d t | x
=========
0 0 0 | 0
0 0 1 | 0
0 1 0 | 0
0 1 1 | 1
1 0 0 | 1
1 0 1 | 0
1 1 0 | 1
1 1 1 | 1

I should also add for those reading this thread that all the above applies to Cyclone III and other devices with 4 input LUTs. Other devices may have LUTs with different designs.